Download Analog circuit design 2007 : sensors, actuators and power by H. Casier, et al., PDF

By H. Casier, et al.,

Analog Circuit layout relies at the each year Advances in Analog Circuit layout workshop. the purpose of the workshop is to collect designers of complicated analogue and RF circuits for the aim of learning and discussing new chances and destiny advancements during this box. chosen issues for AACD 2007 are: (1) Sensors, Actuators and gear Drivers for the automobile and commercial atmosphere (Tue 27 March) - Chaired by means of Herman Casier, AMI Semiconductor Fellow, Belgium (2) built-in PAs from Wireline to RF (Wed 28 March) - Chaired by way of Prof. Michiel Steyaert, Catholic college, Leuven (3) Very excessive Frequency entrance Ends (Thu 29 March) - Chaired by means of Prof. Arthur van Roermund, Eindhoven collage of Technology.
Preface vii
Part I: Sensors, Actuators and gear Drivers for the Automotive
and commercial setting 1
Heterogeneous Integration of Passive parts for the Realization
of RF-System-in-Packages 3
Eric Beyne, Walter De Raedt, Geert Carchon, and Philippe Soussan
The Eye-RIS CMOS imaginative and prescient procedure 15
Ángel Rodríguez-Vázquez, Rafael Domínguez-Castro,
Francisco Jiménez-Garrido, Sergio Morillas, Juan Listán,
Luis Alba, Cayetana Utrera, Servando Espejo and Rafael Romay
An Inductive place Sensor ASIC 33
Petr Kamenicky, Pavel Horsky
CMOS Single-Chip digital Compass with Microcontroller 55
Christian Schott, Robert Racz, Samuel Huber, Angelo Manco,
Markus Gloor, Nicolas Simonne
Protection and prognosis of clever energy High-Side Switches
in car functions 71
Andreas Kucher
Integrated CMOS strength Amplifiers for hugely Linear
Broadband conversation 93
K. Mertens, M. Unterweissacher, M. Tiebout, C. Sandner
Power Combining recommendations for RF and mm-Wave
CMOS energy Amplifiers 115
Patrick Reynaert, M. Bohsali, D. Chowdhury and A. M. Niknejad
Switched RF Transmitters 145
Willem Laflere, Michiel Steyaert and Jan Craninckx
High-Speed Serial stressed Interface for cellular functions 163
Gerrit W. den Besten
High Voltage xDSL Line Drivers in Nanometer applied sciences 179
Bert Serneels, Michiel Steyaert, Wim Dehaene
VoIP SLIC Open Platform: The Wideband Subscriber Line Interface
Luc D’Haeze, Jan Sevenhans, Herman Casier, Damien Macq,
Stefan van Roeyen, Stef Servaes, Geert De Pril, Koen Geirnaert,
Hedi Hakim
Part III: Very excessive Frequency entrance Ends 235
Systems and Architectures for terribly excessive Frequency Radio hyperlinks 237
Peter Baltus, Peter Smulders, Yikun Yu
Key development Blocks for Millimeter-Wave IC Design
in Baseline CMOS 259
Mihai A.T. Sanduleanu, Eduardo Alarcon, Hammad M. Cheema,
Maja Vidojkovic, Reza Mahmoudi and Arthur van Roermund
Analog/RF layout suggestions for High-Power Silicon
Based mmWave and THz purposes 283
Ullrich R. Pfeiffer
SiGe BiCMOS and CMOS Transceiver Blocks for Automotive
Radar and Imaging purposes within the 80-160 GHz variety 303
S.P. Voinigescu, S. Nicolson, E. Laskin, okay. Tang and P. Chevalier
A comparability of CMOS and BiCMOS mm-Wave Receiver
Circuits for purposes at 60GHz and past 327
Sharon Malevsky and John R. Long
Integrated Frontends for Millimeterwave Applications
Using III-V applied sciences 343
Herbert Zirath, Sten E. Gunnarsson, Camilla Kärnfelt, Toru Masuda,
Mattias Ferndahl, Rumen Kozhuharov, Arne Alping

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Extra info for Analog circuit design 2007 : sensors, actuators and power drivers ; integrated power amplifiers from wireline to RF ; very high frequency front ends

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5 ASIC block diagram The second and higher order harmonics from the rectifier and remaining AC common mode signal are filtered by a combined differential/common-mode Low Pass Filter (LPF). The resulting DC signal is in the order of a few mV. Its amplitude varies significantly due to mechanical construction and mechanical tolerances (rotor to stator air gap). To handle such a signal a high performance automatic gain control block is required [5]. A three stage Automatic Gain Control (AGC) block is implemented as shown in Fig.

The most representative among ACE chips instances are collected in Figure 4. 8 GOPs IO: 22Lines Binary 64 x 64 Gray-Scale cells 82 cells/mm2 Pixel Memory: 4 B&W + 4 G Prog. : 32 Templates + 64 Dig. Instructions 40 GOPs IO: 16bit B&W Bus+ 16lines G Bus 128 x 128 Gray-Scale cells 180 cells/mm2 Pixel Memory: 2 B&W + 8 G Prog. : 32 Templates + 4096 Dig. Inst. 190 GOPs IO: 32bit Digital Bus Embedded Data Converters per Column Figure 4: The three generations of ACE chips 22 Á. Rodríguez-Vázquez et al.

In the ACE16k chip, offsets were stored into analog memories which experienced The Eye-RIS CMOS Vision System 27 I/O ADCs I/O DACs System control unit I/O control unit S&H Banks Processing & Sensing Array Generic ADC Temperature sensor Program memory Band-gap & biasing circuitry Programmable analog references Miscellaneous circuitry Figure 9: Block diagram of the Q-Eye chip significant degradation specially at high temperatures. Instead, offsets in the QEye chip are stored in static (non volatile) digital memories.

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